1. Field of the Invention
This invention relates to a semiconductor device and a method for making the same, more particularly to a semiconductor device having an array of pillars and metallic bit lines each of which is connected to a column of slanted bit line contacts extending in a direction slanted relative to a column direction and a row direction of the pillar array.
2. Description of the Related Art
Dynamic random access memory (DRAM) device is a volatile memory device for storing data or information, and includes an array of transistors and capacitors, bit lines electrically coupled to sources or drains of the transistors, and word lines electrically coupled to gates of the transistors. Development of the DRAM devices in the DRAM industry has been focused on how to minimize DRAM chip size. One way of minimizing DRAM chip size is accomplished by forming deep trenches in a Si substrate. The smaller the width of the trenches, the smaller the DRAM chip size will be. However, to reduce the width of the trenches from the current DRAM generation (the width of the trench is about 60 nm) to the next DRAM generation (the width of the trench is about 20-40 nm) can be a great challenge.
FIGS. 1A and 1B illustrate a conventional 4F2 vertical cell type DRAM device that includes: a substrate 1 having a base 11 and a pillar array of pillars 12 extending upwardly from the base 11; a plurality of buried bit lines 13, each of which is embedded in the base 11 and is disposed below and connected to the pillars 12 of a respective one of the columns of the pillar array; a plurality of word lines 14, each of which is connected to middle portions of the pillars 12 of a respective one of rows of the pillar array; an insulator material (not shown) filling gaps among the pillars 12, the buried bit lines 13, and the word lines 14; and a plurality of capacitors 15 disposed on and electrically connected to the pillars 12, respectively.
FIGS. 1C to 1H illustrate consecutive steps of a conventional method of forming the 4F2 DRAM device. The method includes: forming bit line trenches 10 in a semiconductor substrate 1 so as to form the substrate 1 into a base 11 and elongate bars 121 extending upwardly from the base 11 (see FIG. 1C); forming a liner layer 131 on two opposing bar walls of each of the bit line trenches 10 (see FIG. 1D); ion implanting a N+ dopant (such as P, As, or N type ions) into the base 11 at a bottom of each of the bit line trenches 10, followed by annealing or thermal diffusion so as to form a doped region 133 thereat (see FIG. 1E); deepening each of the bit line trenches 10 by dry etching in order to cut each doped region 133 into two separate halves 133a and 133b, thereby forming separated buried bit lines 13 (see FIG. 1F); filling the bit line trenches 10 with a gap fill material 151 (see FIG. 1G); forming a plurality of word line trenches 16, each of which is disposed above and extends across the buried bit lines 13 so as to form each of the elongate bars 121 into a column of pillars 12 (see FIG. 1H), the pillars 12 formed from the elongate bars 121 cooperatively forming a pillar array and being arranged in rows and columns; forming a gate oxide layer (not shown) on sides of each of the pillars 12; forming a plurality of word lines 14, each of which is formed on the gate oxide layer on the sides of the pillars 12 of a respective one of the rows of the pillar array; filling the word line trenches 16 with an insulator material (not shown); and forming a plurality of capacitors (not shown) that are respectively disposed on and electrically connected to the pillars 12.
The conventional method is disadvantageous in that since the doped region 133 thus formed is relatively thick in the depth direction, the bit line trench 10 is required to be deepened an extra depth (e.g., about 200 nm) that is sufficient to cut through the doped region 133, which is very difficult to perform for a narrow space in the trench 10, and that since each buried bit line 13 is made from the dopant which has a relatively low conductivity, the same has a high resistance, which can cause an adverse effect on miniaturization of the DRAM device and hinder the integration of high density of memory cells into each buried bit line 13. In addition, it is relatively difficult to form pick-up contacts or deep position metal silicidate contacts on the buried bit lines 13 in order to reduce the resistance of each buried bit line 13.